High density ASIC cell gate array circuits are known in the art. Such circuits typically replicate a pattern of transistors, and include several layers of insulation and conducting material for interconnecting the transistors. Depending upon the desired application, the ASIC manufacturer determines the circuit functions during fabrication using customized mask layouts. These masks generally require several layers to implement, and define the interconnections between the various transistors within the array. Customizing the various mask layouts for a new or modified ASIC is both time consuming and expensive. This is unfortunate because turnaround time in developing prototype ASIC circuitry is critical in bringing new products to market.
ASIC designers are encouraged to fabricate ever smaller, more densely packed and potentially complex functions within a given chip area. Nonetheless conventional cell designs typically must sacrifice 10% -20% of the chip area to leave room for making interconnections. This dedication of chip area is necessary because some interconnection traces would otherwise traverse an area occupied by a transistor. If a transistor must be located in the area to be traversed, the transistor must first be covered with a layer of insulation, over which a layer of conductive material defining the traversing trace is added. These extra layers are undesirable because they require additional production steps, add to production cost, and decrease production yield. Further, the often tortiously long traverse traces add stray capacitance to the circuit being implemented, and generally diminish circuit performance.
One prior art solution for minimizing traversing interconnects is to combine several cells into larger macro-cells. This solution dedicates the transistors in some macro-cells to certain functions that would otherwise require traverses to implement. For example, a macro-cell containing twenty-six transistors might dedicate six of these transistors to serve as current sources, in anticipation that such current sources will be required by the ASIC (and might otherwise require traversing interconnects for implementation). Thus for this macro-cell, only twenty transistors will be available for customized interconnect (as determined during fabrication), while six transistors are only available for use as current sources. Although this dedication approach minimizes traversing interconnects, in some applications not all of the preformed mini-circuits will be required, with the undesired result that the dedicated transistors are wasted and unavailable for other use.
There is a need for a method of fabricating ASIC cells that permits maximum utilization of the cell chip area, while providing relatively rapid and inexpensive customization. Such a method preferably should not rely upon dedicated transistor connections, thereby increasing the number of transistors in a cell or macro-cell available for customized configuration. Further, such a method should accommodate traversing interconnects. The present invention provides such a method.